The present invention relates to a CMOS type image sensor and, in particular, to an initialization procedure of the A/D within the CMOS type image sensor.
An image sensor is used to transform an optical image focused on the sensor into an electrical signal. The image sensor typically contains an array of light-detecting elements, where each element produces a signal in response to the light intensity impinging on that element when an image is focused on the array. These signals may then be used to display a corresponding image on a monitor.
One very well-known type of image sensor is a charge coupled device (CCD). Integrated circuit chips containing a CCD image sensor are expensive due to the specialized process required. The CCD also consumes a relatively large power dissipation because of the clock signals that are required and the high voltage that is usually needed. In contrast to the CCD image sensor, CMOS active pixel sensors (APS) have attracted much attention recently because of monolithic integration of control, drive and signal process circuitry upon a single sensor chip. The advantages of CMOS APS imagers are: (1) low voltage operation and low power consumption, (2) process compatibility with on-chip electronics, and (3) potentially lower cost as compared to the conventional CCD, because of the wide availability of a standard CMOS manufacturing process.
However, it has been discovered by the inventor that, for large area and high density pixel arrays, the analog signal generated by each light detecting element is subject to varying degrees of parasitic effects such as those caused by parasitic capacitance, resistance, dark current leakage, and non-uniformity of device characteristic. These parasitic effects are inherent in semiconductor devices and result in degradation of the signal-to-noise ratio of the image information. Therefore, noise issues pose a major technical challenge which can limit performance of the CMOS APS. These noises include kTC noise, which is associated with the sampling of the image data, 1/f noise, which is associated with the circuits used to amplify the image signal, and fixed pattern noise which is associated with the non-uniformity between columns within the array.
Even for an identical internal signal at the column line, the device variation, leakage current, and/or mismatching among correlated-double sampling (CDS) circuits and the comparators within the A/D converters in the single integrated circuit CMOS sensor chip will generate different digital signal values at the output of each A/D converter. The variations between the performance of comparators of ADCs and CDS circuits corresponding to cells of different columns are even worse as the line pitch between column lines is shrunk. The invention intends to minimize these parasitic effects of A/D converter and CDS circuits.
An active pixel image sensor fabricated by a CMOS process is described herein, which includes a two-dimensional pixel array core of photo sensing diodes whose conductivities are related to the magnitude of light impinging upon the photodiodes. The analog signals generated by the photodiodes are buffered through a source follower amplifier, accessed by row transistors and coupled to respective columns in the array. The analog signals at each column line are converted to digital signals by an A/D converter (ADC) connected to each column line. Among other methods, the A/D converter may be formed by a high-gain comparator, an 8-bit binary counter coordinated with a reference ramp signal synchronized with a specific timing sequence. A specific timing sequence is used to allow the A/D converter circuit to implement the A/D conversion within a time frame, so that all the sensing elements in a row will have their respective light level converted into a digital value during this interval. The timing might allow the resulting digital values to be delivered to another unctional block of the chip or off the chip for processing during this time also, or perhaps during another time interval. In a preferred embodiment, however, before the read operation of the first line, the potential of the input nodes of CDS on each column line is set up to be a xe2x80x9creferencexe2x80x9d voltage and then its value on each column converted to a digital value through an A/D converter. The resulting output digital data contains information regarding non-uniformity and variation due to the device characteristic variations of A/D converters and CDS circuits. The digital data value corresponding to each output line thus obtained is then used to be the initial value of each ADC counter before following actual A/D operation on a row of the pixel array is performed. Thus, major parasitic effects and distortion for the A/D converters and CDS circuits are minimized during subsequent A/D conversions of actual image.